The Self Boot Engine (SBE) is a small embedded PPE42 core inside the POWER9 CPU which has the unenvious job of getting a single POWER9 core ready enough to start executing instructions out of L3 cache, and poking some instructions into said cache for the core to start executing.<\/p>\n\n\n\n
It’s called the “Self Boot Engine” as in generations prior to POWER8, it was the job of the FSP (Service Processor) to do all of the booting for the CPU. On POWER8, there was still an SBE, but it was a custom instruction set (this was the Power On Reset Engine – PORE), while the PPE42 is basically a 32bit powerpc core cut straight down the middle (just the way to make it awkward for toolchains).<\/p>\n\n\n\n
One of the things I noted in my post on Booting temporary firmware on the Raptor Blackbird<\/a> is that we got serial console output from the SBE. It turns out one of thing things explicitly not<\/strong> enabled by Raptor in their build was this output as “it made the SBE boot much slower”. I’d actually long suspected this, but hadn’t really had the time to delve into it.<\/p>\n\n\n\n Since for POWER9, the firmware for the SBE is now open source<\/a> code, as is the ppe42-binutils<\/a> and ppe42-gcc<\/a> toolchain for it. This means we can hack on it!<\/p>\n\n\n\n WARNING:<\/strong> hacking on your SBE firmware can be relatively<\/em> dangerous, as it’s literally the first thing that needs to work in order to boot the system, and there isn’t (AFAIK) publicly documented easy way to re-flash your SBE firmware if you mess it up.<\/p>\n\n\n\n Seeing as we saw a regression in boot time with the UART output enabled, we need to look at the uartPutChar() function in sbeConsole.C<\/a> (error paths removed for clarity):<\/p>\n\n\n\n One thing you may notice if you’ve spent some time around serial ports is that it’s not using the transmit FIFO! While according to Wikipedia<\/a> the original 16550 had a broken FIFO, but we’re certainly not going to be hooked up to an original rev of that silicon.<\/p>\n\n\n\n To compare, let’s look at the skiboot code, which is all in hw\/lpc-uart.c<\/a>:<\/p>\n\n\n\n The uart_check_tx_room()<\/a> function is pretty simple, it checks if there’s room in the FIFO and knows that there’s 16 entries. Next, we have a busy loop that waits until there’s room again in the FIFO:<\/p>\n\n\n\n Finally, the bit of code that writes the (internal) log buffer out to a serial port:<\/p>\n\n\n\n The skiboot code ends up being a bit more complicated thanks to a number of reasons, but the basic algorithm could be applied to the SBE code, and rather than busy waiting for each character to be written out before sending the other into the FIFO, we could just splat things down there and continue with life. So, I put together a patch to try out<\/a>.<\/p>\n\n\n\n Before (i.e. upstream SBE code): it took about 15 seconds from “Welcome to SBE” to “Booting Hostboot”.<\/p>\n\n\n\n Now (with my patch): Around 10 seconds.<\/p>\n\n\n\n It’s a full five seconds (33%) faster to get through the SBE stage of booting. Wow.<\/p>\n\n\n\n Hopefully somebody looks at the pull request<\/a> sometime soon, as it’s probably useful to a lot of people doing firmware and Operating System development.<\/p>\n\n\n\n So, Happy New Year for Blackbird owners (I’ll publish a build with this and other misc improvements “soon”).<\/p>\n","protected":false},"excerpt":{"rendered":" The Self Boot Engine (SBE) is a small embedded PPE42 core inside the POWER9 CPU which has the unenvious job of getting a single POWER9 core ready enough to start executing instructions out of L3 cache, and poking some instructions … Continue reading static void uartPutChar(char c)\n{\n #define SBE_FUNC \"uartPutChar\"\n uint32_t rc = SBE_SEC_OPERATION_SUCCESSFUL;\n do {\n static const uint64_t DELAY_NS = 100;\n static const uint64_t DELAY_LOOPS = 100000000;\n\n uint64_t loops = 0;\n uint8_t data = 0;\n do {\n rc = readReg(LSR, data);\n...\n if(data == LSR_BAD || (data & LSR_THRE))\n {\n break;\n }\n delay(DELAY_NS, 1000000);\n } while(++loops < DELAY_LOOPS);\n\n...\n rc = writeReg(THR, c);\n...\n } while(0);\n\n #undef SBE_FUNC\n}<\/code><\/pre>\n\n\n\nstatic void uart_check_tx_room(void)\n{\n\tif (uart_read(REG_LSR) & LSR_THRE) {\n\t\t\/* FIFO is 16 entries *\/\n\t\ttx_room = 16;\n\t\ttx_full = false;\n\t}\n}<\/code><\/pre>\n\n\n\nstatic void uart_wait_tx_room(void)\n{\n\twhile (!tx_room) {\n\t\tuart_check_tx_room();\n\t\tif (!tx_room) {\n\t\t\tsmt_lowest();\n\t\t\tdo {\n\t\t\t\tbarrier();\n\t\t\t\tuart_check_tx_room();\n\t\t\t} while (!tx_room);\n\t\t\tsmt_medium();\n\t\t}\n\t}\n}<\/code><\/pre>\n\n\n\n\/*\n * Internal console driver (output only)\n *\/\nstatic size_t uart_con_write(const char *buf, size_t len)\n{\n\tsize_t written = 0;\n\n\t\/* If LPC bus is bad, we just swallow data *\/\n\tif (!lpc_ok() && !mmio_uart_base)\n\t\treturn written;\n\n\tlock(&uart_lock);\n\twhile(written < len) {\n\t\tif (tx_room == 0) {\n\t\t\tuart_wait_tx_room();\n\t\t\tif (tx_room == 0)\n\t\t\t\tgoto bail;\n\t\t} else {\n\t\t\tuart_write(REG_THR, buf[written++]);\n\t\t\ttx_room--;\n\t\t}\n\t}\n bail:\n\tunlock(&uart_lock);\n\treturn written;\n}<\/code><\/pre>\n\n\n\n